1. Field of the Invention
The present invention relates to a lateral diffused metal-oxide-semiconductor field-effect transistor structure, and more particularly, to a lateral diffused metal-oxide-semiconductor field-effect transistor in which a P substrate and an N epitaxial layer are isolated by an N+ buried layer.
2. The Prior Art
As the semiconductor industry develops, high power components are often applied in many aspects of power electronics. Since a lateral diffused metal-oxide-semiconductor field-effect transistor (LDMOS) is more easily compatible with the complementary metal-oxide-semiconductor (CMOS) process, thus LDMOS is widely used.
Referring to FIG. 1, a view of LDMOS according to prior art is shown. As shown in FIG. 1, LDMOS 1 according to prior art includes a P substrate 10, a P+ buried layer 12, an N epitaxial layer 30, a P well 40, an N well 50, a drain region, a source region, and a body region, wherein the P+ buried layer 12 is located between the P substrate 10 and the P well 40, and the N epitaxial layer 30 is on the P substrate 10.
The N well 50 is in the N epitaxial layer 30, and the drain region is on the N well 50. The drain region includes a high voltage N drain layer 62 and an N+ drain layer 64. The N+ drain layer 64 is on the high voltage N drain layer 62 and connects with a plurality of drain terminals D.
The drain region and the body region are located in P well 40. The source region includes a high voltage N source layer 72 and an N+ source layer 74. The N+ source layer 74 is on the high voltage N source layer 72 and connects with a plurality of source terminals S. The body region includes P+ body contact layer 82 and connects with a plurality of body terminals B.
LDMOS 1 also includes a thick oxide isolation region 92 and a P bottom isolation layer 94 and thereby avoids high voltage connection lines (not shown) on the thick oxide isolation region 92 to accidentally turn on the N epitaxial layer 30 under the P bottom isolation layer 94.
LDMOS 1 also includes a protective layer 110, which covers a drain region, a source region, a body region, and a thick oxide isolation region 92, for providing protection.
Generally speaking, when LDMOS is turned on, the drain terminals D connect to a high voltage, such as 600 V, the source terminals S is grounded, and a positive voltage higher than a threshold voltage of the LDMOS 1 is applied to the body terminals B. Accordingly, the LDMOS 1 is turned on, and a high current flows from the drain terminals D to the source terminals S. Therefore, an on-resistance Ron from the drain terminals D to the source terminals S is the smaller the better, so as to make the ohmic consumption power lower, reduce a rise of the temperature of LDMOS, and improve the lifetime and the reliability of components. The plurality of drain terminals D are used to increase the effective width of channels, which is a commonly used method for reducing on-resistance. In addition, it may also reduce a distance between the drain region and the source region to achieve the purpose of reducing on-resistance. However, there may be a negative effect of lowering breakdown voltage.
When LDMOS 1 is turned off, the drain terminals D connect with a high voltage (600 V), and the source terminals S and the body terminals B are grounded, so that the LDMOS 1 is turned off. At this time, the connection lines (not shown) connecting with the drain terminals D have a high voltage of 600 V, and a breakdown between the drain region and the source region of LDMOS 1 may happen so that LDMOS 1 fails or is even permanently damaged. Although the thick oxide isolation region 92 may improve protection, the effect is still quite limited. As a result, an LDMOS structure which may ensure PN junction breakdown not occur is needed.